Accelerating architectural simulation by parallel execution of trace samples

In order to quickly decide which architectural features are to be included in future processors the author has developed a simulation approach that samples benchmark program instruction traces. Rather than simulating an architecture with the entire SPEC92 program suite of more than 100 billion instructions, he simulates using a set of samples of the SPEC92 suite containing less than 1% of the total instruction trace. Each of the samples contains a short instruction trace that can be simulated quickly. By distributing the simulation of the samples across many workstations he is able to carry out architectural simulations in less than one half hour. The sample set is verified to be representative of the complete instruction trace using several metrics. The technique described can be applied to existing architectural models to produce significant reductions in simulation time.<>