Performance of the RamLink memory architecture

RamLink is a proposal by the P1596.4 IEEE working group for defining a high bandwidth memory architecture. A RamLink memory system consists of a memory controller and a number of memory chips connected in a ring topology. The signaling rate of the ring is two nanoseconds and the data lane is eight bits wide. The RamLink memory controller implements a packet based protocol to issue read/write requests to the memory chips. The RamLink protocol supports concurrent transfers, making performance prediction more difficult than that of typical memory interfaces. Therefore, we have built a detailed simulation model of both the memory chips and a memory controller. Using the simulator we can observe protocol behavior under various memory read/write access scenarios. The focus of our research is to verify the expected performance of RamLink and to identify limitations in the RamLink protocol. The authors wish to emphasize that this paper presents performance simulations: the details of the RamLink architecture are specified by the IEEE working group. We also compare RamLink to a high bandwidth memory system using a buslike architecture.<>