DocumentCode
2068851
Title
An algorithm for area and delay optimisation of sequential machines through decomposition
Author
Dasgupta, Aurobindo ; Koren, Israel
Author_Institution
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Volume
1
fYear
1994
fDate
4-7 Jan. 1994
Firstpage
36
Lastpage
45
Abstract
Presents a new algorithm for decomposing a Finite State Machine (FSM) to reduce the area and delay. For a known state encoding, it partitions the next state and output bits so as to decrease the cost, which is a function of the area and delay. A state encoding which yields a low cost is derived by using a heuristic algorithm. This algorithm differs from existing algorithms in that it uses a measure for the area that is more reflective of the actual area of the final chip.<>
Keywords
circuit CAD; finite state machines; logic CAD; sequential circuits; sequential machines; Finite State Machine; area optimisation; delay optimisation; final chip; sequential machines; state encoding;
fLanguage
English
Publisher
ieee
Conference_Titel
System Sciences, 1994. Proceedings of the Twenty-Seventh Hawaii International Conference on
Conference_Location
Wailea, HI, USA
Print_ISBN
0-8186-5090-7
Type
conf
DOI
10.1109/HICSS.1994.323187
Filename
323187
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