A three-stage LDO with active feedback frequency compensation and slew-rate enhancement

Author

Tongning Hu ; Bo Wang ; Ke Lin ; Yi Peng ; Xin´an Wang

Author_Institution

Shenzhen Grad. Sch., Key Lab. of Integrated Microsyst., Peking Univ., Shenzhen, China

fYear

2013

fDate

28-31 Oct. 2013

Firstpage

1

Lastpage

4

Abstract

This paper presents a low drop-out (LDO) regulator using an active feedback frequency compensation (AFFC) structure for compensation. By eliminating the right-half-plane zero and bringing a left one, the phase margin and the stability can be improved. And the compensation loop reuses the current in the first stage to minimize the quiescent current. A slew-rate enhancement circuit is presented to speed up transient response. The LDO regulator provides full range stability from 0 to 100mA load current. The LDO is simulated in a 0.18um CMOS process, supplying 1.6V with a dropout voltage of 181mV. The quiescent current is 29uA for 100pF load capacitor.

Keywords

CMOS integrated circuits; compensation; voltage regulators; AFFC structure; CMOS process; active feedback frequency compensation; capacitance 100 pF; compensation loop; current 0 mA to 100 mA; current 29 muA; low drop-out regulator; phase margin; quiescent current minimization; right-half-plane zero elimination; size 0.18 mum; slew-rate enhancement circuit; three-stage LDO regulator; transient response; voltage 1.6 V; voltage 181 mV; Capacitors; Circuit stability; Q-factor; Regulators; Stability analysis; Transient analysis; Transient response;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC (ASICON), 2013 IEEE 10th International Conference on

Conference_Location

Shenzhen

ISSN

2162-7541

Print_ISBN

978-1-4673-6415-7

Type

conf

DOI

10.1109/ASICON.2013.6812035

Filename

6812035