• DocumentCode
    2068899
  • Title

    A DLL based low-phase-noise clock multiplier with offset-tolerant PFD

  • Author

    Yuwen Wang ; Fan Ye ; Junyan Ren

  • Author_Institution
    State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
  • fYear
    2013
  • fDate
    28-31 Oct. 2013
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    This paper presents design techniques of a low-jitter delay-locked loop (DLL) based clock multiplier. The DLL is designed to generate 12 phases and a multiplied output in a continuous lock range from 40MHz to 110 MHz. A novel transecting PFD is introduced to prevent static phase offset. The core occupies an active area of 0.008 mm2 in a 65nm CMOS process and consumes 950uW from a supply voltage of 1.2V.
  • Keywords
    CMOS digital integrated circuits; clocks; delay lock loops; frequency multipliers; integrated circuit design; phase noise; CMOS process; DLL based low-phase-noise clock multiplier; frequency 40 MHz to 110 MHz; low-jitter delay-locked loop; offset-tolerant PFD; phase-frequency detector; power 950 muW; size 65 nm; static phase offset; transecting PFD; voltage 1.2 V; Clocks; Computer architecture; Delays; Jitter; Phase frequency detector; Phase locked loops; Synchronization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC (ASICON), 2013 IEEE 10th International Conference on
  • Conference_Location
    Shenzhen
  • ISSN
    2162-7541
  • Print_ISBN
    978-1-4673-6415-7
  • Type

    conf

  • DOI
    10.1109/ASICON.2013.6812037
  • Filename
    6812037
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2068899