DocumentCode :
2069110
Title :
Ultra-low noise and high PSR LDO design
Author :
Jiangpeng Wang ; Jinguang Jiang
Author_Institution :
Sch. of Electron. Inf., Wuhan Univ., Wuhan, China
fYear :
2013
fDate :
28-31 Oct. 2013
Firstpage :
1
Lastpage :
4
Abstract :
This paper presents a new ultra-low noise and high PSR LDO structure. This structure can achieve ultra-low noise performance without large filter capacitor by incorporating a capacitance amplifying circuit in the structure of LDO with pre-regulation. A large amount of chip area will be saved in this structure. Also this structure can achieve high PSR under a wide frequency range by introducing a feed-forward path between the drain and gate of the pass transistor. A novel LDO in proposed structure is realized under SMIC 0.18μm process. The experimental results show that proposed LDO structure can achieve a total output noise of 25.5μV between 10Hz-1KHz and 56.4μV between 1KHz-1MHz with a filter capacitor of 5pF. PSR is -71.6dB under low frequency until 49KHz and at least -65.7dB under entire frequency range.
Keywords :
feedforward; integrated circuit design; voltage regulators; LDO design; PSR; capacitance 5 pF; capacitance amplifying circuit; feedforward path; frequency 1 kHz to 1 MHz; frequency 10 Hz to 1 kHz; low dropout regulator; pass transistor; power supply rejection; size 0.18 mum; ultra-low noise performance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC (ASICON), 2013 IEEE 10th International Conference on
Conference_Location :
Shenzhen
ISSN :
2162-7541
Print_ISBN :
978-1-4673-6415-7
Type :
conf
DOI :
10.1109/ASICON.2013.6812044
Filename :
6812044
Link To Document :
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