Title :
A 1.8-V 14-bit inverter-based incremental ΣΔ ADC for CMOS image sensor
Author :
Biao Wang ; Meng Zhang ; Xu Cheng ; Qi Feng ; Xiaoyang Zeng
Author_Institution :
Dept. of Microelectron., Fudan Univ., Shanghai, China
Abstract :
This paper presents a 14-bit 100-kHz bandwidth incremental sigma-delta analog-to-digital converter suitable for CMOS image sensors with column-parallel ADCs. By using an inverter instead of an operational trans-conductance amplifier (OTA), the total assumption of modulator is dramatically reduced. To further decrease the power consumption, a body bias inverter is proposed in the inverter, enhancing the current efficiency gm/IDS. Since the decimating filter can be realized with a much simpler structure, a full custom circuit design is applied to the schematic design with a self-timing control cell. The proposed single-ended incremental ADC is designed in 0.18μm CMOS technology. The simulation result shows that for a 1.8V supply, 30MHz sampling frequency and 150 oversampling ratio, the power consumption is 122.2μW, dynamic range is 85dB and the ENOB is 13.26bit.
Keywords :
CMOS image sensors; logic gates; sigma-delta modulation; CMOS image sensor; analog-digital converter; column parallel ADC; incremental sigma-delta ADC; inverter based sigma-delta ADC; power 122.2 muW; single ended incremental ADC; size 0.18 mum; voltage 1.8 V; CMOS image sensors; CMOS integrated circuits; Clocks; Computer architecture; Inverters; Modulation; Power demand;
Conference_Titel :
ASIC (ASICON), 2013 IEEE 10th International Conference on
Conference_Location :
Shenzhen
Print_ISBN :
978-1-4673-6415-7
DOI :
10.1109/ASICON.2013.6812046