A 4-mW8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DAC

A 4-mW 8-b 600-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is simulated in a standard 65-nm CMOS. By adopting reference capacitive DAC, four-input comparator and the data calibration unit, the proposed ADC could achieve higher speed. As simulated at sampling rate of 600 MS/s, the proposed ADC could achieve a peak SNR of 52.7 dB and maintain ENOB higher than 7.5 bits up to 302-MHz input signal frequency. The FoM of proposed ADC is 34.5 fJ/conversion-step at a 600-MS/s sampling rate and a 1.2-V supply.