Analog/RF performance evaluation of nanoscale non-overlap SOI MOSFETs with high-k stack on spacer

In this work, the potential of non-overlap (also known as gate-underlap) source/drain (S/D) extension region (spacer s) design using high-k dielectric stack on spacer of Silicon-on-Insulator (SOI) MOSFETs has been discussed to improve the analog/RF performances. The results obtained from 2D-ATLAS device simulator show that high-k dielectric spacer reduces the short-channel effects (SCEs) by ≅ 22% as well as improves the on-to-off current ratio I_on/I_off by nearly three times compared to conventional (air) spacer design. Furthermore for analog/RF performances simulation results reveal an improvement of voltage gain A_v by ≅ 72%, gain bandwidth (GBW) by ≅75% an increase of ≅40% and ≅25% in the case of cut-off frequency f_T and maximum frequency of oscillation f_MAX values respectively, of SOI MOSFETs with high-k stack on spacer compared to conventional spacer. In this work the results of I_on and I_off with nitride stack on spacer compare very favorably with both current International Technology Roadmap for Semiconductors (ITRS-2011) specifications and available experimental data for SOI MOSFETs.