DocumentCode
2069495
Title
ESD-sensitive LNA design
Author
Xin Wang ; Lin Lin ; Wang, Aiping ; Li-Wu Yang ; Xiaokang Guan ; Guang Chen ; Hongyi Chen ; Yumei Zhou ; Hainan Liu ; Bin Zhao
Author_Institution
Dept. of Electr. Eng., Univ. of California, Riverside, CA
fYear
2008
fDate
19-23 May 2008
Firstpage
156
Lastpage
159
Abstract
A new ESD-sensitive LNA design method is presented, featuring S-parameter modelling and input matching network re-matching techniques for ESD+LNA full-chip design optimization. Design of 5 GHz LNA with 5 kV ESD protection in a 0.18 mum RFCMOS technology shows ESD-induced performance reduction in gain and noise figure up to -14.3% and +18% over a 1.8 GHz bandwidth range, which can be recovered by +76.3% and 63%, respectively, by using the proposed design technique.
Keywords
CMOS analogue integrated circuits; MMIC amplifiers; S-parameters; electrostatic discharge; integrated circuit design; low noise amplifiers; ESD-sensitive LNA design; RFCMOS technology; S-parameter modelling; frequency 1.8 GHz; frequency 5 GHz; input matching network rematching techniques; size 0.18 mum; voltage 5 kV; Electromagnetic compatibility; Fabrication;
fLanguage
English
Publisher
ieee
Conference_Titel
Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, 2008. APEMC 2008. Asia-Pacific Symposium on
Conference_Location
Singapore
Print_ISBN
978-981-08-0629-3
Electronic_ISBN
978-981-08-0629-3
Type
conf
DOI
10.1109/APEMC.2008.4559835
Filename
4559835
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