A novel method for delay analysis of CMOS inverter with on-chip RLC interconnect load

Author

Maheshwari, V. ; Mazumdar, Subhra ; Kar, Rajib ; Mandal, Durbadal ; Bhattacharjee, A.K.

Author_Institution

Dept. of ECE, Apeejay Stya Univ., Gurgaon, India

fYear

2012

fDate

17-19 Dec. 2012

Firstpage

1

Lastpage

3

Abstract

In this paper, the behaviour of CMOS inverter driving RLC interconnect load is analyzed. The analysis is based on the modelling of RLC load, developed for submicron devices. Sakurai´s alpha-power law is used here for representing the transistor current. Accurate and analytical expressions for the output voltage waveform are derived by solving the system of differential equations which describe the behaviour of the circuit. The 50% delay for on-chip interconnect is then calculated from the transient response. The output response derived from this model is compared with the SPICE simulation results and the results obtained by using the proposed model are in good agreement with SPICE model. The maximum error has been found to be 9.4%.

Keywords

CMOS integrated circuits; RLC circuits; SPICE; differential equations; invertors; transient response; transistors; CMOS inverter; SPICE simulation; Sakurai alpha-power law; delay analysis; differential equation; on-chip RLC interconnect load; submicron device; transient response; transistor current; voltage waveform; Delay calculation; Interconnect; RLC Load; VLSI;

fLanguage

English

Publisher

ieee

Conference_Titel

Computers and Devices for Communication (CODEC), 2012 5th International Conference on

Conference_Location

Kolkata

Print_ISBN

978-1-4673-2619-3

Type

conf

DOI

10.1109/CODEC.2012.6509268

Filename

6509268