Within-clock power gating architecture implimentation to reduce leakage

With the technology scaling leakage power has become comparable to dynamic power. Power gating is a technique which is used to reduce standby leakage by shutting down the power supply of the inactive block of the circuit. There is also scope of using power gating in active block to reduce run time leakage. Within clock period there is certain portion which is idle and in this period power gating may be used. In this paper we present this within-clock power gating for minimizing leakage and total power of the sequential circuits during active mode of operation. The technique is used to implement the architecture of ISCAS89 benchmark circuit. Power results have been reported for different frequency. Simulation of the implemented architecture in CADENCE VLSI tool at 45nm technology shows leakage saving of 73% and 54.78% saving in switching compared to the designs without within-clock power gating at 1.25 MHZ.