Study of substrate induced strained-Si/SiGe channel for optimizing CMOS digital circuit characteristics

In this work, the prospect of designing CMOS based digital electronic circuits incorporating strained-Si/Si_1-xGe_x MOSFETs is studied. The fundamental drawback in designing CMOS digital circuits is the compulsion of maintaining a larger width of the p-MOS in respect to its n-MOS counterpart. This is due to the fact that the hole and electron mobilities are not equal. The scale factor of the p-MOS transistor, however, depends on whether the circuit is optimized for robustness or high speed; the choice of one obviously compromises the other performance metric. In this context, incorporation of a strained-Si p-MOS in such a circuit is expected to improve the performance in terms of speed as well as noise margin. We have analyzed the characteristics of CMOS inverters using a combination of strained-Si p- and conventional-Si n- channel CMOS inverters for different compositions of Ge in the virtual substrate (VS) and have determined that the two conflicting scaling requirements can converge when the Ge content in VS is ~ 40%.