DocumentCode :
2070197
Title :
Effect of flip chip package architecture on stresses in the bump passivation opening
Author :
Karajgikar, Saket ; Nagaraj, Vishal ; Agonafer, Dereje
Author_Institution :
Dept. of Mech. & Aerosp. Eng., Univ. of Texas, Arlington, TX
fYear :
2009
fDate :
26-29 May 2009
Firstpage :
936
Lastpage :
942
Abstract :
In this paper, a non-linear analysis is performed in detail to study the effect of package architectural attributes such as die thickness, die size, substrate thickness, substrate size and passivation opening (PO) size on the stress induced in the bump during reflow process is studied in detail. A commercially available finite element analysis tool is used to evaluate the stresses induced in the bump (at the PO) due to the coefficient of thermal expansion(CTE) mismatch during the standard reflow process. Based on the numerical analysis of the legs of the DOE, the stress in the PO can vary between 7 KPa to 138 KPa. The bumps with small PO size exhibited higher stress than the bumps with large PO size. For the bumps with small PO size, the stress contours are lateral bands where as in case of the bumps with large PO size, high stress is noted at the periphery which diminishes towards the center. The packages with thick substrate and die exhibited higher stress than packages with thin substrate and die. Also, the effect of ratio of substrate size to die size on the stress in the PO was found to be insignificant. Previously, the current authors have reported the effect of various bump parameters on the current density in the bump as well as in the trace. These effects of bump parameters are combined with the effects of package architectural attributes and enhanced guidelines are presented.
Keywords :
chip scale packaging; finite element analysis; flip-chip devices; passivation; stress analysis; thermal expansion; thermal management (packaging); bump parameters; bump passivation opening; die size; die thickness; finite element analysis tool; flip chip package architecture; nonlinear analysis; numerical analysis; pressure 7 kPa to 138 kPa; standard reflow process; stress effects; substrate size; substrate thickness; thermal expansion coefficient; Finite element methods; Flip chip; Leg; Numerical analysis; Packaging; Passivation; Performance analysis; Thermal expansion; Thermal stresses; US Department of Energy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 2009. ECTC 2009. 59th
Conference_Location :
San Diego, CA
ISSN :
0569-5503
Print_ISBN :
978-1-4244-4475-5
Electronic_ISBN :
0569-5503
Type :
conf
DOI :
10.1109/ECTC.2009.5074125
Filename :
5074125
Link To Document :
بازگشت