HW/SW architecture co-synthesis of ASIP-based MPSoCs for highly- demanding applications

Summary form only given. The recent spectacular progress in modern nano-dimension semiconductor technology enabled implementation of a very complex multi-processor system on a single chip (MPSoC), mobile and autonomous computing, global networking and wire-less communication, and facilitated a fast progress in these areas. New important opportunities have been created. The traditional applications can be served much better and numerous new sorts of embedded systems became technologically feasible and economically justified. Various monitoring, control, communication or multi-media systems that can be put on or embedded in (mobile, poorly accessible or distant) objects, installations, machines or devices, or even implanted in human or animal body can serve as examples. However, many of the modern embedded application impose very stringent functional and parametric demands. Moreover, the spectacular advances in microelectronics introduced unusual silicon and system complexity. The combination of the huge complexity with the stringent application requirements results in numerous serious design and development challenges, such as: accounting in design for more aspects and related complex multi-objective MPSoC optimization, adequate resolution of numerous complex design tradeoffs, reduction of the design productivity gap for the increasingly complex and sophisticated systems, reduction of the time-to market and development costs without compromising the system quality, etc. These challenges cannot be well addressed without an adequate system and design methodology adaptation. The first part of the presentation is devoted to discussion of the serious issues and challenges in development of contemporary and future demanding embedded systems and introduction of the quality-driven model-based design methodology proposed by the presenter. Subsequently, the Intel´s ASIP-based MPSoC technology is introduced, and a new automatic design flow for heterogeneous ASIP- based MPSoCs- is discussed, when focusing on the system and processor level design- space exploration (DSE) involving coherent HW/SW architecture co-synthesis, macro- and micro-architecture design tradeoff exploitation, and application-specific memory and communication design. This flow and its EDA tools are results from the European research project ASAM (Automatic Architecture Synthesis and Application Mapping for MPSoCs based on adaptable ASIPs) performed in the framework of the industrial research program ARTEMIS. The final presentation part overviews several methods and EDA-tools of the ASAM flow focusing on the micro-architecture level DSE involving the application analysis and parallelization, ASIP micro-architecture synthesis and application scheduling and mapping, combined in one coherent HW/SW co-synthesis process.