Determining the test sources/sinks for NoC TAMs

Author

Amory, Alexandre ; Moreno, E. ; Moraes, Filipe ; Lubaszewski, Marcelo S.

Author_Institution

FACIN, PUCRS Univ., Porto Alegre, Brazil

fYear

2013

fDate

5-7 Aug. 2013

Firstpage

8

Lastpage

13

Abstract

Conventional approaches using the Network-on-Chip (NoC) as Test Access Mechanism (TAM), called NoC TAM, model the test sources/sinks and the routing algorithm as constraints to the test scheduling, reducing its efficiency. This paper is based on a new NoC TAM model where these constraints do not exist, potentially resulting in shorter tests. The contribution of this paper is to present the part of the test flow which determines the optimal number and location of the test sources and sinks in a NoC TAM without constraining the test scheduler. Searching the minimal number of sources/sinks can minimize the silicon area overhead since each NoC source/sink requires about 4300 gates for a NoC channel with 32-bit width.

Keywords

logic testing; network routing; network-on-chip; silicon; NoC TAM model; NoC channel; Si; network-on-chip; routing algorithm; silicon area overhead; storage capacity 32 bit; test access mechanism; test scheduling; test sources/sinks; Gold; Switches; System-on-chip; SoC test; VLSI test; networks-on-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI (ISVLSI), 2013 IEEE Computer Society Annual Symposium on

Conference_Location

Natal

ISSN

2159-3469

Type

conf

DOI

10.1109/ISVLSI.2013.6654615

Filename

6654615