An efficient modelling technique for computing the parasitic capacitances in VLSI circuits

Author

Ning, Zhen-Qiu ; Dewilde, Patrick M.

Author_Institution

Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands

fYear

1988

fDate

7-9 June 1988

Firstpage

1131

Abstract

An efficient method is presented to model the parasitic capacitance of VLSI interconnections. The model approximates the charge density on the conductors as a continuous function on a web of edges. Each base function in the approximation has the form of a spider of edges. The authors show that the model: (1) has very low complexity as compared to previously presented models; and (2) achieves a high degree of precision within the range of validity of the stratified medium.<>

Keywords

VLSI; capacitance; circuit analysis computing; equivalent circuits; VLSI circuits; VLSI interconnections; charge density; continuous function; degree of precision; low complexity; modelling technique; parasitic capacitance computation; spider of edges; stratified medium; web of edges; Conductors; Dielectrics; Geometry; Integral equations; Integrated circuit interconnections; Parasitic capacitance; Piecewise linear approximation; Piecewise linear techniques; Shape; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1988., IEEE International Symposium on

Conference_Location

Espoo, Finland

Type

conf

DOI

10.1109/ISCAS.1988.15125

Filename

15125

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2070755