Towards Real Time Parallelism Reduction for Digital UWB Receiver

The mostly digital ultra wideband (UWB) receiver, designed for worst case channel conditions, uses significant parallelism in the digital backend which increases power consumption. However, the wireless channel may vary due to factors such as time delay and channel impulse response. This paper investigates and analyses effects of these factors on receiver parallelism for determining sufficient hardware required for different channel conditions. This analysis is performed for exploring real time parallelism reduction to save power in the digital backend of the UWB receiver. The paper also discusses the functional blocks and design constraints of one of the parallelism reduction algorithm.