An estimation method of chip level power distribution network inductance using full wave simulation and segmentation method

An impedance profile of power distribution network (PDN) in system is an efficient criterion to evaluate the system performance in high-speed and high-performance semiconductor system design. Especially, PDN inductance estimation is more important because high impedance occurs at high frequency bandwidth with larger inductance and it generates larger simultaneous switching noise. In this paper, we propose a new calculation method to extract the inductance of chip level PDN based on full wave simulation and segmentation method. We fabricated two kinds of chip level PDN and measured the impedance profiles of test vehicles in the frequency domain up to 20 GHz so as to verify the proposed estimation method.