Title :
A high speed BiCMOS table look-up gate
Author :
Baltus, Peter ; Van der Meulen, Pieter S. ; Ligthart, Michiel
Author_Institution :
Philips Res., Sunnyvale, CA, USA
Abstract :
The authors describe a BiCMOS programmable gate array (PGA) with subnanosecond logic block delay and low power consumption. Each logic block can implement any Boolean function of three inputs, a D-latch, or an SR-latch. The PGA is supported by an advanced design environment, which includes schematic capture, interactive functional simulation, logic minimization, and technology mapping
Keywords :
BIMOS integrated circuits; Boolean functions; logic CAD; logic arrays; logic gates; table lookup; BiCMOS; Boolean function; D-latch; SR-latch; design environment; high-speed gate; interactive functional simulation; logic minimization; low power consumption; programmable gate array; schematic capture; subnanosecond logic block delay; table look-up gate; technology mapping; Application specific integrated circuits; BiCMOS integrated circuits; Delay; Electronics packaging; Feedback; Logic devices; Logic gates; MOSFETs; Power generation; Programmable logic arrays;
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
DOI :
10.1109/CICC.1991.164037
