DocumentCode
2071091
Title
Cost effective dry lithography solution for through silicon via technology
Author
Jacquet, F. ; Henry, D. ; Charbonnier, J. ; Bouzaida, N. ; Sillon, N. ; Raine, J.S.
Author_Institution
CEA, MINATEC, Grenoble
fYear
2009
fDate
26-29 May 2009
Firstpage
1170
Lastpage
1176
Abstract
In this paper, an original way to open buried contact in TSV via-last process using dry film lithography will be presented. This approach may solve at the same time issues on either non tapered vias and sloped vias technologies. In the first part of the paper the via-last process flow and the technological issues will be briefly described. Then the contact opening lithography using dry film will be presented. This includes mask design, process parameters and morphological characterization. In the third part of the paper, we will show some results and characterization of the contact etching step. For process evaluation, this brick was implemented in our CIS wafer level packaging process flow and some electrical test were performed.
Keywords
CMOS image sensors; etching; films; lithography; masks; resists; wafer level packaging; CIS wafer level packaging process flow; CMOS image sensors; contact etching step; dry film lithography; electrical test; mask design; through silicon via technology; Computational Intelligence Society; Contacts; Costs; Etching; Lithography; Paper technology; Process design; Silicon; Through-silicon vias; Wafer scale integration; Advanced packaging; Dry Film Resist (DFR); Through Silicon Via (TSV); Via-last; Wafer level technologies;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference, 2009. ECTC 2009. 59th
Conference_Location
San Diego, CA
ISSN
0569-5503
Print_ISBN
978-1-4244-4475-5
Electronic_ISBN
0569-5503
Type
conf
DOI
10.1109/ECTC.2009.5074160
Filename
5074160
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