TPI for improving PR fault coverage of Boolean and three-state circuits

Author

Geuzebroek, M.J. ; van de Goor, A.J.

Author_Institution

Fac. of Inf. Technol. and Syst., Delft Univ. of Technol., Netherlands

fYear

2003

fDate

25-28 May 2003

Firstpage

3

Lastpage

8

Abstract

TPI (test point insertion) can be used to improve the pseudo-random testability of circuits. However, many TPI algorithms are based on COP, which can only cope with Boolean circuits, while in the industry three-state circuits are also found. In this paper the testability analysis method COP, and the COP based HCRF TPI algorithm, are extended with three-state capabilities, and the HCRF TPI algorithm is adjusted in such a way that better PR (pattern resistant) fault coverage improvements can be achieved for Boolean as well as for three-state circuits.

Keywords

built-in self test; design for testability; logic testing; ternary logic; BIST; Boolean circuits; COP testability analysis method; HCRF TPI algorithm; circuit pseudo-random testability; cost function; pattern resistant fault coverage; test point insertion; three-state circuits; Algorithm design and analysis; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Fault detection; Hardware; Switches; System testing; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Workshop, 2003. Proceedings. The Eighth IEEE European

ISSN

1530-1877

Print_ISBN

0-7695-1908-3

Type

conf

DOI

10.1109/ETW.2003.1231661

Filename

1231661