• DocumentCode
    2071139
  • Title

    A novel tool flow for increased routing configuration similarity in multi-mode circuits

  • Author

    Al Farisi, Brahim ; Vansteenkiste, Elias ; Bruneel, Karel ; Stroobandt, Dirk

  • Author_Institution
    ELIS Dept., Ghent Univ., Ghent, Belgium
  • fYear
    2013
  • fDate
    5-7 Aug. 2013
  • Firstpage
    96
  • Lastpage
    101
  • Abstract
    A multi-mode circuit implements the functionality of a limited number of circuits, called modes, of which at any given time only one needs to be realised. Using run-time reconfiguration (RTR) of an FPGA, all the modes can be time-multiplexed on the same reconfigurable region, requiring only an area that can contain the biggest mode. Typically, conventional run-time reconfiguration techniques generate a configuration of the reconfigurable region for every mode separately. This results in configurations that are bit-wise very different. Thus, in this case, many bits need to be changed in the configuration memory to switch between modes, leading to long reconfiguration times. In this paper we present a novel tool flow that retains the placement of the conventional RTR flow, but uses TRoute, a reconfiguration-aware connection router, to implement the connections of all modes simultaneously. DRoute stimulates the sharing of routing resources between connections of different modes. This results in a significant increase in the similarity between the routing configurations of the modes. In the experimental results it is shown that the number of routing configuration bits that needs to be rewritten is reduced with a factor between 2 and 4 compared to conventional techniques.
  • Keywords
    field programmable gate arrays; network routing; DRoute; FPGA; TRoute; configuration memory; conventional RTR flow; conventional techniques; multimode circuits; reconfigurable region; reconfiguration times; reconfiguration-aware connection router; routing configuration similarity; routing configurations; routing resources; run-time reconfiguration techniques; time-multiplexing; tool flow; Benchmark testing; Field programmable gate arrays; Multiplexing; Routing; Switches; Table lookup; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI (ISVLSI), 2013 IEEE Computer Society Annual Symposium on
  • Conference_Location
    Natal
  • ISSN
    2159-3469
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2013.6654629
  • Filename
    6654629