DocumentCode
2071148
Title
Parity-based output compaction for core-based SOCs [logic testing]
Author
Sinanoglu, Ozgur ; Orailoglu, Alex
Author_Institution
Comput. Sci. & Eng. Dept., Univ. of California San Diego, La Jolla, CA, USA
fYear
2003
fDate
25-28 May 2003
Firstpage
15
Lastpage
20
Abstract
SOC test application time is strongly determined by the parallelism attained among core tests. Yet, test bandwidth allocation issues typically impose significant limitations on parallel testing of the cores. In this paper, we propose a response compaction methodology for reducing the required output bandwidth of cores, enabling increased parallelism among core tests and hence reducing overall SOC test time. The proposed methodology is based on judiciously partitioning test responses, with each response fragment being compacted individually. The signature corresponding to the response fragments consists of the parity information which is computed through a cost-effective on-chip space and time compaction mechanism. We show that the proposed technique not only delivers negligible aliasing for any (modeled or unmodeled) fault but that it also provides diagnostic and unknown response value handling capabilities.
Keywords
boundary scan testing; logic design; logic testing; system-on-chip; bandwidth allocation; core test parallelism; core-based SOC; diagnostics; fault aliasing; logic testing; parallel core testing; parity-based output compaction; response compaction; response fragment signature; scan-based SOC test; test response partitioning; unknown response value handling; Application software; Bandwidth; Channel allocation; Circuit faults; Circuit testing; Compaction; Computer science; Parallel processing; Test data compression; Transportation;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Workshop, 2003. Proceedings. The Eighth IEEE European
ISSN
1530-1877
Print_ISBN
0-7695-1908-3
Type
conf
DOI
10.1109/ETW.2003.1231663
Filename
1231663
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