Electrical performance assessment of advanced substrate technologies for high speed networking applications

High end computing and networking applications continue to drive silicon technologies for higher performance, increased bandwidth and frequency. The drive for higher performance has resulted in increased power dissipation. A method for mitigating power dissipation includes reducing the voltage but unfortunately the consequence is reduced noise margin. This paper evaluates the electrical performance and assess the design trade-offs of two new advanced packaging concepts designed to improve the PDN (Power Delivery Network) in a typical ASIC (Application Specific Integrated Circuit) by introducing features for enhancing core power decoupling and decreasing inductance and impedance in the organic substrate. A baseline test chip was redesigned into two advanced package configurations: (1) a package utilizing a conventional 4-4-4 substrate with SMT components mounted between the BGA (Ball Grid Array) balls, and (2) a package utilizing a 9+1 coreless substrate. A volume production 40 mm times 40 mm BGA package with a 14 times 14 mm functional test chip assembled onto a standard build-up 4-4-4 substrate running different traffic patterns in a networking device was used as the baseline for comparison Substrate level, package level and system level electrical performance tests were performed. Models for power plane impedance and core power noise were extracted using PowerSI and simulated using HSPICE for each new technology and compared to the baseline ASIC. Special test points were designed onto the substrates and custom lids were used to facilitate measurements of the power noise under different traffic patterns and payloads. All results were compared with the production baseline component design.