Title :
Debug architecture for system on chip taking full advantage of the test access port
Author :
Moerman, E. ; Bocq, S. ; Verfaillie, J.
Author_Institution :
Design Departement JA, Alcatel Fixed Network Div., Antwerp, Belgium
Abstract :
This paper describes the architecture of a structural, cost effective debug methodology, applicable to a system on chip in its system environment and targeting software as well as hardware debugging. The highly modular and flexible architecture enables an almost infinite variation of flexible configurable modules designed and hooked up to the test access port (TAP). The hardware configuration flexibility is supported by software running on a PC or workstation, hooked up via a POD connected to the TAP interface. The result is an easy to use implementation of increased observability.
Keywords :
computer debugging; design for testability; logic testing; open systems; system-on-chip; POD TAP interface; SoC debug architecture; SoC system environment; configurable test modules; design for debug; hardware debugging; observability; open debug architecture; software debugging; system on chip debug; test access port; Computer architecture; Costs; Design for disassembly; Digital signal processing; Hardware; Observability; Software debugging; System testing; System-on-a-chip; Workstations;
Conference_Titel :
Test Workshop, 2003. Proceedings. The Eighth IEEE European
Print_ISBN :
0-7695-1908-3
DOI :
10.1109/ETW.2003.1231683
