A yield-driven regular layout synthesis

The continuous devices shrinking has introduced new challenges to integrated circuit design, mainly to deal with the overall yield loss (Beckett 2002). Designers start to take into account process variability impact in the early design stages to successful deal with yield loss. Process variability have a critical effect on integrated circuits increasing power consumption to out of design specifications, accelerating circuit degradation or introducing erroneous circuit functionality. Routing ... This work proposes two main contributions to improve yield: explore regular detailed routing reducing the number of vias and explore new approaches of basic cells in a regular layout synthesis.