On analyzing and mitigating SRAM BER due to random thermal noise

Embedded memory is a major design element in microprocessors and system-on-chips. Typically embedded memories are constituted of SRAM circuits. SRAM cell stability is a major determinant of V_min for ultra-low power mobile computing. At low voltages, thermal noise plays a role in SRAM cell stability. In this work, we present an analysis of random thermal noise on stability of SRAM bit cells. Of specific concern to us, is the process of device aging, where a transistor performance may degrade over time. A marginal SRAM bit cell that is stable at the time of manufacturing test may become susceptible to random bit flips due to thermal noise under aging related degradation. In order to quantify the impact of random thermal noise on SRAM cell stability, we present a methodology to measure the expected Random Bit Error Rate (BER). Such analysis helps select minimum supply voltage to meet target BER. Next we propose selective multi-level WL control for access transistors of marginal cells to improve their stability during read and write operations. Simulation studies show a BER of ~1 per 10⁶ reads at a low operating voltage of 700mV. The proposed design techniques reduce probability of random bit errors to nearly zero at marginal performance penalty. Application of stochastic analysis to a sample 2MB cache shows >10X improvement in BER and hence improved longevity of marginal cells.