An Analog DS-UWB receiver

In this paper, we propose a direct-conversion direct-sequence inductorless CMOS receiver for pulse-based UWB communications using a high-speed analog Viterbi decoder. The circuit system architecture is presented and simulation results for a four-stage RC-oscillator, a low-noise amplifier, a down-conversion mixers and the analog Viterbi decoder are provided, which are critical building blocks in our receiver. The LNA with the passive mixers achieves a maximum voltage gain of 18 dB, -23 dBV IIP3 and the noise figure (NF) of 2.1. Our target is a 125 Mbit/s at the distance of 10 m using a 1 GHz bandwidth dedicated to UWB systems between 3.1-4.9 GHz utilizing the analog Viterbi decoder. Proposed radio architecture makes possible high-speed communication with decreased power consumption.