DocumentCode
2072550
Title
Over 10-times high-speed, energy efficient 3D TSV-integrated hybrid ReRAM/MLC NAND SSD by intelligent data fragmentation suppression
Author
Chao Sun ; Fujii, Hiromitsu ; Miyaji, K. ; Johguchi, Koh ; Higuchi, Kenichi ; Takeuchi, Ken
Author_Institution
Dept. of Electr., Electron. & Commun. Eng., Chuo Univ., Tokyo, Japan
fYear
2013
fDate
22-25 Jan. 2013
Firstpage
81
Lastpage
82
Abstract
A 3D through-silicon-via (TSV)-integrated hybrid ReRAM/multi-level-cell (MLC) NAND solid-state drive´s (SSD´s) architecture is proposed with NAND-like interface (I/F) and sector-access overwrite policy for ReRAM. Furthermore, intelligent data management algorithms are proposed to suppress data fragmentation and excess usage of MLC NAND. As a result, 11-times performance increase, 6.9-times endurance enhancement and 93% write energy reduction are achieved. Both ReRAM write and read latency should be less than 3 μs to obtain these improvements. The required endurance for ReRAM is 105.
Keywords
NAND circuits; flash memories; random-access storage; three-dimensional integrated circuits; 3D through-silicon-via-integrated hybrid ReRAM/multi-level-cell NAND solid-state drive architecture; NAND-like interface; ReRAM write and read latency; endurance enhancement; energy efficient 3D TSV-integrated hybrid ReRAM/MLC NAND SSD; intelligent data fragmentation suppression; intelligent data management algorithms; sector-access overwrite policy; write energy reduction; Educational institutions; Flash memories; Heuristic algorithms; Random access memory; Reliability; Three-dimensional displays; Through-silicon vias;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific
Conference_Location
Yokohama
ISSN
2153-6961
Print_ISBN
978-1-4673-3029-9
Type
conf
DOI
10.1109/ASPDAC.2013.6509566
Filename
6509566
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