Title :
A 3Gb/s 2.08mm2 100b error-correcting BCH decoder in 0.13µm CMOS process
Author :
Youngjoo Lee ; Hoyoung Yoo ; In-Cheol Park
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea
Abstract :
This paper presents a high-throughput BCH decoder that can correct 100 bit-errors. Several optimization methods are proposed to reduce the hardware complexity caused by the large error-correction capability. Based on the proposed methods, an 8-parallel decoder is designed for the (9592, 8192, 100) BCH code, which achieves a decoding throughput of 3Gb/s and occupies 2.08mm2 in 0.13μm CMOS process.
Keywords :
CMOS digital integrated circuits; codecs; error correction codes; 100 BCH code; 8192 BCH code; 9592 BCH code; CMOS process; bit rate 3 Gbit/s; error correcting BCH decoder; error correction capability; high throughput BCH decoder; parallel decoder; size 0.13 mum; Complexity theory; Computer architecture; Decoding; Hardware; Logic gates; Polynomials; Throughput;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-1-4673-3029-9
DOI :
10.1109/ASPDAC.2013.6509568
