Title :
A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS
Author :
Zhixiang Chen ; Xiao Peng ; Xiongxin Zhao ; Okamura, L. ; Dajiang Zhou ; Goto, Satoshi
Author_Institution :
Grad. Sch. of Inf., Production & Syst, Waseda Univ., Kitakyushu, Japan
Abstract :
An LDPC decoder in 65nm CMOS targeting WPAN (IEEE 802.15.3c) is presented with measurement results. A modified-PCM based message permutation strategy with compatible data flow is proposed to solve the network problem raised by high parallelism LDPC decoding. Compared to the state-of-art, decoder chip achieves 17.7%, 33.5% and 49% improvements in chip density, gate count and energy efficiency, respectively.
Keywords :
CMOS integrated circuits; codecs; parity check codes; personal area networks; telecommunication standards; CMOS; IEEE 802.15.3c; WPAN LDPC decoder; bit rate 6.72 Gbit/s; chip density; data flow; decoder chip; energy efficiency; gate count; high parallelism LDPC decoding; message permutation strategy; network problem; size 65 nm; Decoding; Energy efficiency; IEEE 802.15 Standards; Logic gates; Parity check codes; Phase change materials; Registers;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-1-4673-3029-9
DOI :
10.1109/ASPDAC.2013.6509569
