DocumentCode :
2072788
Title :
A full 4-channel 60 GHz direct-conversion transceiver
Author :
Kawai, Shigeaki ; Minami, Ryutaro ; Musa, Afiqah ; Sato, Takao ; Ning Li ; Yamaguchi, Toru ; Takeuchi, Yoshio ; Tsukui, Y. ; Okada, Kenichi ; Matsuzawa, Akira
Author_Institution :
Dept. Phys. Electron., Tokyo Inst. of Technol., Tokyo, Japan
fYear :
2013
fDate :
22-25 Jan. 2013
Firstpage :
95
Lastpage :
96
Abstract :
This paper presents a 60-GHz direct-conversion transceiver in 65 nm CMOS technology. By the proposed gain peaking technique, this transceiver realizes good gain flatness and is capable of more than 7 Gbps in 16QAM wireless communication for all channels of IEEE802.11ad standard within EVM of around -23 dB. The transceiver consumes 319mWin transmitting and 223mW in receiving, including the PLL consumption.
Keywords :
CMOS integrated circuits; quadrature amplitude modulation; transceivers; wireless LAN; CMOS technology; EVM; IEEE 802.11ad standard; PLL consumption; bit rate 7 Gbit/s; direct-conversion transceiver; frequency 60 GHz; gain flatness; gain peaking technique; power 223 mW; power 319 mW; size 65 nm; wireless communication; CMOS integrated circuits; Gain; Mixers; Noise measurement; Phase locked loops; Radio frequency; Transceivers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific
Conference_Location :
Yokohama
ISSN :
2153-6961
Print_ISBN :
978-1-4673-3029-9
Type :
conf
DOI :
10.1109/ASPDAC.2013.6509573
Filename :
6509573
Link To Document :
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