A sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceivers

Author

Siriburanon, Teerachot ; Wei Deng ; Musa, Afiqah ; Okada, Kenichi ; Matsuzawa, Akira

Author_Institution

Dept. Phys. Electron., Tokyo Inst. of Technol., Tokyo, Japan

fYear

2013

fDate

22-25 Jan. 2013

Firstpage

97

Lastpage

98

Abstract

A 58.1-to-65.0 GHz frequency synthesizer using sub-harmonic injection-locking technique is presented. The synthesizer can generate all 60GHz channels defined by IEEE 802.15.3c, wirelessHD, IEEE 802.11ad, WiGig, and ECMA-387. A frequency calibration scheme is proposed to monitor frequency shift resulting from environmental variations. Implemented in a 65nm CMOS process, the synthesizer achieves a typical phase noise of -117 dBc/Hz @10MHz offset from a carrier frequency of 61.56 GHz.

Keywords

CMOS integrated circuits; calibration; frequency synthesizers; radio transceivers; CMOS process; ECMA-387; IEEE 802.11ad; IEEE 802.15.3c; TDD transceivers; WiGig; environmental variations; frequency 58.1 GHz to 65.0 GHz; frequency calibration scheme; frequency shift monitoring; phase noise; sub-harmonic injection-locked frequency synthesizer; sub-harmonic injection-locking technique; wirelessHD; Calibration; Frequency synthesizers; Mixers; Phase locked loops; Phase noise; Synthesizers;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific

Conference_Location

Yokohama

ISSN

2153-6961

Print_ISBN

978-1-4673-3029-9

Type

conf

DOI

10.1109/ASPDAC.2013.6509574

Filename

6509574