FPGA Design of onboard queue management equipment based on occupancy

This paper designs onboard queue management equipment based on occupancy due to the limitation of hardware procession speed and memory capacity on the satellite onboard ATM switch. It utilizes the previous address pointer (PAP) and the next address pointer (NAP) to control the writing and reading of the cell, and implement queue occupancy policy. The results of ModelSim timing simulation show that it satisfies the design of the queue management equipment, and has high stability.