A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC

Author

Yoshioka, Kazuaki ; Shikata, Akira ; Sekimoto, Ryota ; Kuroda, Tadahiro ; Ishikuro, Hiroki

Author_Institution

Keio Univ., Yokohama, Japan

fYear

2013

fDate

22-25 Jan. 2013

Firstpage

111

Lastpage

112

Abstract

An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple V_cm biased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V.

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); constant current sources; low-power electronics; CMOS; SNDR; area efficient 2bit/step operation; asynchronous SAR ADC; biased current sources; comparator threshold; extremely-low power SAR ADC; power efficient 2bit/step operation; power supply variation; prototype ADC; single supply voltage; size 40 nm; voltage 0.35 V to 0.8 V; wide range dynamic threshold configuring comparator; word length 8 bit; Calibration; Capacitance; Capacitors; Noise; Power supplies; Prototypes; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific

Conference_Location

Yokohama

ISSN

2153-6961

Print_ISBN

978-1-4673-3029-9

Type

conf

DOI

10.1109/ASPDAC.2013.6509581

Filename

6509581