Realizing near-true voltage scaling in variation-sensitive L1 caches via fault buffers

Voltage scaling can be applied to cache memories to reduce their energy consumptions. However, reduced supply voltage to the cache memories increases defective SRAM cells due to process variations, which will decrease their yields and performance nullifying the benefits of voltage scaling. To mitigate this problem, we propose a fault buffer-based scheme for L1 caches. Faults are identified and isolated at the granularity of individual words in the L1 caches. Actively used faulty cache words are allocated in the fault buffers dynamically. The fault buffers are organized as multiple banks for low cost implementation and can be reconfigured dynamically to reflect varying performance demands of programs. This dynamic scheme is shown to be more energy- and area-efficient than, and to be performing comparably to the previously proposed static schemes.