DocumentCode
2073587
Title
2.6 Gbyte/sec bandwidth cache/TLB macro for high-performance RISC processor
Author
Takayanagi, T. ; Sawada, Kazuhiro ; Takahashi, Makoto ; Ito, Yukiko ; Uchida, Masanori ; Toyoshima, Yoshiaki ; Hayashida, Hiroyuki ; Norishima, Masayuki
Author_Institution
Toshiba Corp., Kawasaki, Japan
fYear
1991
fDate
12-15 May 1991
Abstract
The authors describe an on-chip cache/TLB macro which can be integrated with highly concurrent RISC (reduced instruction set computer) processors. The macro incorporates TLB, a 16-kbyte instruction cache, and a 16-kbyte two-port data cache. It executes virtual-to-physical address translation and following physical cache access in 12 ns. The total bandwidth is 2.6 Gbyte/s at 80 MHz. A test chip was fabricated with 0.5-μm double-polysilicon triple-metal CMOS technology
Keywords
CMOS integrated circuits; buffer storage; integrated memory circuits; microprocessor chips; reduced instruction set computing; 0.5 micron; 12 ns; 16 kByte; 2.6 GByte/s; 80 MHz; RISC processor; double-polysilicon triple-metal CMOS technology; reduced instruction set computer; Bandwidth; CMOS technology; Clocks; Indium tin oxide; Microelectronics; Microprocessors; Reduced instruction set computing; Semiconductor devices; Testing; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0015-7
Type
conf
DOI
10.1109/CICC.1991.164046
Filename
164046
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