Conformal polymer edge interconnect method for high capacity high performance packages for solid state storage applications

While much work is being expended throughout the industry on expensive, TSV (through-silicon-via) approaches, the intent of the work reported here was to thoroughly characterize the performance and reliability of a lower cost, non-disruptive, easier to implement improvement to wire bond and TSV methods that offers broad usefulness for many applications today. Our work focused on 3D packaging for memory cards, smart phones, and solid state storage devices to minimize footprint and maximize memory capacity. By varying temperature, cure time, and order of occurrence in the process sequence, we were able to optimize the adhesion of the polymer conductors to the contacts on the die and minimize resistance. Conductor resistance of less than 0.2 ohms/mm were observed. The 3D stacks of flash memory die fabricated with this technique allowed us to reduce SSD volume by 75%, resulting in a 4X increase in memory density.