Title :
FPGA performance versus cell granularity
Author :
Kouloheris, Jack L. ; El Gamal, Abbas
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA, USA
Abstract :
An experimental approach was used to investigate the relationship between the performance of an FPGA (field-programmable gate array) and its basic cell granularity. Over a large set of design examples it was found that a four or five input cell achieves minimum average critical path delay for a wide range of programmable switch time constant, τ s. As expected, the `optimal´ cell granularity was found to increase gradually as τs increases
Keywords :
delays; logic arrays; FPGA performance; cell granularity; critical path delay; delay model; field-programmable gate array; Boolean functions; CMOS technology; Contracts; Delay effects; Field programmable gate arrays; Latches; Lifting equipment; Routing; Switches; Wire;
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
DOI :
10.1109/CICC.1991.164048
