DocumentCode
2074235
Title
Circuit-compatible modeling of carbon nanotube FETs in the ballistic limit of performance
Author
Raychowdhury, Arijit ; Mukhopadhyay, Saibal ; Roy, Kaushik
Author_Institution
Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Volume
1
fYear
2003
fDate
12-14 Aug. 2003
Firstpage
343
Abstract
Carbon Nanotube Field-Effect Transistors (CNFETs) are being extensively studied as possible successors to CMOS. Novel device structures have been fabricated and device simulators have been developed to estimate their performance in a sub-10 nm transistor era. This paper presents a novel circuit-compatible modeling of CNFETs in their ultimate performance limit. The model so developed has been used to simulate arithmetic and logic blocks using HSPICE.
Keywords
carbon nanotubes; field effect transistors; logic gates; semiconductor device models; 10 nm; C; CMOS; FET; arithmetic blocks; ballistic limit; carbon nanotube; carbon nanotube field effect transistors; circuit compatible modeling; logic blocks; Capacitance; Carbon nanotubes; Circuit simulation; Computational modeling; Delay estimation; Electrostatics; Logic; Numerical models; SPICE; Semiconductor device modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Nanotechnology, 2003. IEEE-NANO 2003. 2003 Third IEEE Conference on
Print_ISBN
0-7803-7976-4
Type
conf
DOI
10.1109/NANO.2003.1231788
Filename
1231788
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