Underfills for lead-free and low-k flip chip packages

The introduction of lead-free bumps into flip chip packages in combination with the incorporation of Cu / low-k or ultra low-k dielectric materials is making underfill development more challenging. The traditional concept of stiff and rigid underfills does not satisfy the new device reliability requirements. Rather, newer generation underfill materials need to balance the physical properties, such as Tg (glass transition temperature), CTE (coefficient of thermal expansion), and modulus etc., to overcome the internal stresses built into the flip chip system. In this paper, a series of underfills with a wide range of underfill properties, such as Tg of 50degC - 130degC, CTE1 of 16 ppm/degC - 40ppm/degC, modulus of 6GPa - 12GPa, were developed and evaluated on lead-free fine pitch flip chip packages. The results showed that an underfill with a middle range of Tg, a lower CTE and a moderate modulus enhances the device´s reliability and can pass JEDEC L3/260degC, 1000 cycle TCB without any underfill delamination. In addition, some common issues associated with advanced underfills, such as underfill voids, flow, flux compatibility, warpage, etc. will be discussed in this study.