Design tradeoffs in speculative Transactional memory architecture

Author

Wang, Yaobin ; Liu, Zhiqin ; Wu, Mingyan ; Wang, Fupan ; An, Hong

Author_Institution

Dept. of Comput. Sci. & Technol., Southwest Univ. of Sci. & Technol., Mianyang, China

fYear

2011

fDate

16-18 Dec. 2011

Firstpage

1341

Lastpage

1344

Abstract

Combining the benefits of Thread level speculation (TLS) and Transactional memory (TM) can enhance the performance of chip multiprocessor (CMP) effectively. This paper proposes a novel speculative transactional memory architecture “SPT” that supports both TLS&TM semantics, including its special hardware, compiler and execution support. It further trades off several important factors in the multicore architecture design. The experimental results show that 16 cache lines is the proper speculative buffer capacity and the write back strategy is the better cache design choice in speculation.

Keywords

cache storage; memory architecture; microprocessor chips; multi-threading; multiprocessing systems; performance evaluation; program compilers; CMP performance enhancement; SPT architecture; TLS semantics; TM semantics; cache lines; chip multiprocessor; compiler support; design tradeoffs; execution support; multicore architecture design; speculative buffer capacity; speculative transactional memory architecture; thread level speculation; write back strategy; Encapsulation; Hardware; Instruction sets; Multicore processing; Parallel processing; multicore; thread level speculation; transactional memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Transportation, Mechanical, and Electrical Engineering (TMEE), 2011 International Conference on

Conference_Location

Changchun

Print_ISBN

978-1-4577-1700-0

Type

conf

DOI

10.1109/TMEE.2011.6199454

Filename

6199454