HS3DPG: Hierarchical simulation for 3D P/G network

Author

Shuai Tao ; Xiaoming Chen ; Yu Wang ; Yuchun Ma ; Yiyu Shi ; Hui Wang ; Huazhong Yang

Author_Institution

Tsinghua Nat. Lab. for Inf. Sci. & Technol. (TNList), Tsinghua Univ., Beijing, China

fYear

2013

fDate

22-25 Jan. 2013

Firstpage

509

Lastpage

514

Abstract

As different chips are stacked together in 3D ICs, the power/ground (P/G) network simulation becomes more challenging than that of 2D cases. In this paper, we propose a hierarchical simulation method suitable for 3D P/G network (HS3DPG), which can ensure full parallelism and good scalability with the number of tiers. In the IR drop analysis, when there are 9 tiers, the hierarchical method can be 6.5 times faster than the direct full network simulation. The accuracy of HS3DPG has been verified by a 3D P/G network from the industrial design. Besides, we introduce the “locality” property into HS3DPG to further simplify the simulation. Finally, HS3DPG is used to analyze the voltage distribution of a 3D P/G network with clustered TSVs.

Keywords

integrated circuit modelling; three-dimensional integrated circuits; 3D IC; 3D P/G network; HS3DPG; IR drop analysis; clustered TSV; full parallelism; good scalability; hierarchical simulation method; power/ground network simulation; through silicon via; Computational modeling; Integrated circuit modeling; Jacobian matrices; Ports (Computers); Solid modeling; Three-dimensional displays; Through-silicon vias; 3D P/G network; hierarchical simulation; port equivalent model;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific

Conference_Location

Yokohama

ISSN

2153-6961

Print_ISBN

978-1-4673-3029-9

Type

conf

DOI

10.1109/ASPDAC.2013.6509647

Filename

6509647