Interference investigation of entire power distribution system from chip, package to board for high speed IO design

In this paper, the analysis of the power distribution system(PDS), including chip, package and board, was presented for system level design in the high-speed IO application. The integrated-analysis methodology was to link different scale physical geometries in an interactive platform. Instead of using the traditional time-domain simulation, the IO power distribution system characteristics were analyzed through frequency domain impedances, taking into account the coupling of simultaneously switching of adjacent IO cells. Finally, PDS intra-interference within one power domain and inter-one between two interfaces were characterized for the physical implementation guidance.