Full exploitation of process variation space for continuous delivery of optimal delay test quality

The increasing magnitude of process variations individualizes effectively each chip, necessitating distinct quantities of test resources for each in order to optimize overall delay test quality without exceeding set test budgets. This paper proposes an analytical framework that delivers the optimal test time assignment per chip in order to minimize the delay defect escape rate. Adjustment of the chip-specific test time in the continuous process variation space is attained through an adaptive test flow that utilizes process data measurements from the device under test. The results evince that a substantial improvement in the delay test quality can be obtained at no increase whatsoever to test time consumed by conventional test flows.