On Design of Efficient Comb Decimator with Improved Response for Sigma-Delta Analog-to-Digital Converters

This paper focuses on the design of multiplier-free comb decimator for the sigma-delta (Sigma-Delta) analog-to-digital converters (ADCs), with the aims of improving the circuit performance and magnitude response simultaneously. Based on the polyphase decomposition and modified prime factorization, the comb decimation filter in the proposed structure can be implemented with lower power consumption and higher speed compared with the traditional comb decimation filter. Further more, the application of the interpolated second-order polynomials (ISOP) filter can significantly reduce the passband droop with little impact on the aliasing attenuation.