NETHDL: abstraction of schematics to high-level HDL

This paper discusses NETHDL, a system for automatic generation of high-level RTL models from switch-level circuit netlist descriptions. NETHDL abstracts several difficult constructs into high-level code using a powerful algorithmic translation which does not sacrifice logic accuracy. NETHDL recognizes constructs such as busses, feedback loops, memory elements, registers, blocks of pass-transistor logic and elements containing contention. NETHDL exploits information from its static circuit analyzer to obtain a highly abstracted model with the same functionality as the netlist. It also uses information about the circuit such as structure, hierarchy and functionality in the generation process. New algorithms are proposed and have been implemented. In all exercised circuits, a significant speedup has been obtained in simulator run-time