From double to triple gate: Modeling junctionless nanowire transistors

Author

Cardoso Paz, Bruna ; Pavanello, Marcelo Antonio ; Casse, Mikael ; Barraud, Sylvain ; Reimbold, Gilles ; Faynot, Olivier ; Avila-Herrera, Fernando ; Cerdeira, Antonio

Author_Institution

Dept. of Electr. Eng., Centro Univ. da FEI, São Bernardo do Campo, Brazil

fYear

2015

fDate

26-28 Jan. 2015

Firstpage

5

Lastpage

8

Abstract

This paper presents a continuous, physically and charge-based new model for triple gate junctionless nanowire transistors (3G JNT). The presented model was evolved from a previous one designed for double gate junctionless transistors (2G JNT). The capacitance coupling and the internal potential changing from 2G to 3G JNTs are considered. The model validation is performed through both numerical simulation and experimental measurements for long and short channel devices.

Keywords

capacitance; nanowires; semiconductor device models; semiconductor junctions; transistors; capacitance coupling; internal potential changing; long channel devices; short channel devices; triple gate junctionless nanowire transistors; Capacitance; Degradation; Electric fields; Electric potential; Logic gates; Numerical models; Transistors; Junctionless; measurements; modeling; simulation; triple gate;

fLanguage

English

Publisher

ieee

Conference_Titel

Ultimate Integration on Silicon (EUROSOI-ULIS), 2015 Joint International EUROSOI Workshop and International Conference on

Conference_Location

Bologna

Type

conf

DOI

10.1109/ULIS.2015.7063759

Filename

7063759