A multiscale modeling and experimental study of underfill flow and void formation for flip-chip packages

This paper uses a validated, two-dimensional global underfill flow model previously developed by the authors [1] to examine the effects of substrate surface (ceramic vs. organic) and temperature-dependent underfill viscosity on underfill flow-out time, flow front shape, and void formation during the flip chip encapsulation process. Model predictions are validated by experiments using bumped quartz dies that allow for direct visualization of the underfill infiltration process. In addition, a full three-dimensional underfill flow model is developed to quantify the effect of slanted and convex-shaped solder bumps. The filler particle inhomogeneity due to settling and shear migration is also accounted for in the model. The present study seeks to provide a comprehensive understanding of concurrent effects in the flip-chip underfilling process.